Staff Physical Design Engineer

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Staff Physical Design Engineer based in the United States. This role offers the opportunity to lead the physical implementation of next-generation semiconductor chips supporting advanced AI computing applications. You will translate sophisticated microarchitectures into high-performance, power-efficient silicon, owning designs from netlist through foundry tapeout. The position combines hands-on physical design expertise with technical leadership across block-level and top-level implementation. You will tackle challenging timing, power, area, and signal integrity requirements using industry-standard EDA tools. Collaboration with design, verification, and foundry teams will be central to achieving robust and manufacturable results. You will also help improve physical design methodologies and automation flows to accelerate future chip development. This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Staff Physical Design Engineer based in the United States. This role offers the opportunity to lead the physical implementation of next-generation semiconductor chips supporting advanced AI computing applications. You will translate sophisticated microarchitectures into high-performance, power-efficient silicon, owning designs from netlist through foundry tapeout. The position combines hands-on physical design expertise with technical leadership across block-level and top-level implementation. You will tackle challenging timing, power, area, and signal integrity requirements using industry-standard EDA tools. Collaboration with design, verification, and foundry teams will be central to achieving robust and manufacturable results. You will also help improve physical design methodologies and automation flows to accelerate future chip development. Accountabilities: Lead block-level and top-level physical design activities, including floorplanning, placement, clock tree synthesis, and routing. Drive designs toward aggressive performance, power, and area (PPA) targets through advanced timing closure techniques. Analyze and resolve power integrity challenges, including electromigration (EM), IR drop, and power grid verification. Develop and maintain Tcl and Python automation scripts to improve physical design flows, methodologies, and engineering efficiency. Work closely with physical verification teams to ensure designs meet applicable rules and implementation requirements. Collaborate with foundry teams to address physical design requirements and support successful tapeout execution. Contribute to physical design methodology development, flow setup, and evaluation of advanced implementation approaches. Provide technical leadership on complex physical implementation challenges and help drive designs through the complete development lifecycle. Requirements: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline. 10–15 years of dedicated professional experience in semiconductor physical design. Extensive experience with EDA implementation flows, particularly Cadence design tools. Strong understanding of static timing analysis (STA) and advanced timing closure methodologies. Proven experience delivering both block-level and top-level physical designs; hierarchical floorplanning experience is a strong advantage. Solid knowledge of low-power design techniques, physical debugging, EM/IR analysis, and power grid verification. Strong scripting capabilities in Tcl or Python for design flow automation. Understanding of advanced semiconductor process nodes and physical verification requirements associated with routing and implementation. Experience establishing and evaluating physical design methodologies and implementation flows. Familiarity with PDK management and semiconductor foundry tapeout processes is highly desirable. Strong analytical, problem-solving, communication, and cross-functional collaboration skills. Benefits: Remote opportunity available across the United States and Canada. Annual salary range of $170,000–$240,000 USD for U.S.-based employees. Annual salary range of $170,000–$230,000 CAD for Canada-based employees. Actual compensation is determined based on job-related knowledge, skills, and experience. Opportunity to work on advanced semiconductor technologies and next-generation AI computing systems. High-impact technical role with significant ownership across physical implementation and tapeout activities. How Jobgether works: We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team. We appreciate your interest and wish you the best! Why Apply Through Jobgether? Data Privacy Notice: By submitting your application, you acknowledge that Jobgether will process your personal data to evaluate your candidacy and share relevant information with the hiring employer. This processing is based on legitimate interest and pre-contractual measures under applicable data protection laws (including GDPR). You may exercise your rights (access, rectification, erasure, objection) at any time. #LI-CL1